1. Technical Field
The invention relates generally to semiconductor devices and more specifically to ESD protection for semiconductor devices.
2. Related Art
Electrostatic discharge (ESD), a surge in voltage (negative or positive) that occurs when a large amount of current is applied to an integrated circuit, may cause substantial damage to the circuit. ESD events are particularly troublesome for BiCMOS RF (radio frequency) chips because of their low power requirements and extreme sensitivity. On-chip ESD protection circuits for BiCMOS chips are essential. Generally, though, such circuits require a high failure threshold and a small layout size.
Low loading capacitance and small chips will require ESD protection to assist in the discharge of current through the analog or RF chip. Furthermore, since power domains are separated for noise isolation in mixed signal applications such as RF applications, ESD power clamps are important in providing good ESD protection. To discharge ESD impulses, a ESD protection scheme needs a low voltage turn-on and a high current drive.
Accordingly, a need has developed in the art for a ESD structure that will provide ESD protection in RF or similar applications.
The present invention provides a ESD power clamp circuit that allows ESD protection for semiconductor chips through a power clamping device. The power clamping device includes a FET and a bipolar element. The power clamping device has a buried diffusion, which is used as a subcollector for the bipolar element, and is used as an isolation for the FET.
Generally, the present invention provides an ESD power clamp circuit comprising:
a trigger circuit;
a delay circuit coupled to said trigger circuit; and
a power clamping device, coupled to said delay circuit, said power clamping device including
an FET formed in an isolated region;
a bipolar element formed in said isolated region;
a substrate of a first doping type; and
a buried diffusion of a second doping type opposite said first doping type, said buried diffusion being a subcollector for said bipolar element, and said buried diffusion being an isolation for said FET.
In addition, the present invention provides a method for protecting a ESD power clamp circuit from electrostatic discharge comprising the steps of:
a) providing a substrate of a first doping type on said chip;
b) providing a buried diffusion of a second doping type;
c) isolating a region of a first doping type from said substrate with said buried diffusion;
d) forming a FET in said isolated region; and
e) forming a bipolar element in said isolated region with said buried diffusion being a subcollector for said bipolar element.
The present invention also provides a system having an ESD power clamp circuit comprising:
at least two power rails;
a trigger circuit;
a delay circuit coupled to said trigger circuit; and
a power clamping device coupled to said delay circuit, said power clamping device including
an FET in an isolated region;
a bipolar element in said isolated region;
a substrate of a first doping type; and
a buried diffusion of a second doping type opposite said first doping type, said buried diffusion being a subcollector for said bipolar element, and said buried diffusion being an isolation for said FET.
The foregoing and other features of the invention will be apparent from the following more particular description of embodiments of the invention, as illustrated in the accompanying drawings.